B. Chess. Improving Computer Security using Extended Static Checking. IEEE Symposium on Security and Privacy, 2002.
B. Chess, T. Larrabee. Creating Small Fault Dictionaries. IEEE Transactions on Computer-Aided Design, pages 346-356 , 1999.
D. B. Lavo, B. Chess, T. Larrabee, and I. Hartanto. Probabilistic Mixed-Model Fault Diagnosis. In Proceedings of the International Test Conference, pages 1084-1093, 1998.
Jayashree Saxena, Hari Balachandran, Kenneth Butler, D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson. On Applying Non-Classical Defect Models to Automated Diagnosis. In Proceedings of the International Test Conference, pages 748-757, 1998.
B. Chess, T. Larrabee. Testing Bridging Faults in CMOS Integrated Circuits. IEEE Transactions on Computers, pages 338-345, March 1998.
D. B. Lavo, B. Chess, T. Larrabee, and F. J. Ferguson, Diagnosing Realistic Bridging Faults with Single Stuck-At Information. IEEE Transactions on Computer-Aided Design, pages 255-268, March 1998.
D. B. Lavo, B. Chess, T. Larrabee, F. J. Ferguson, Jayashree Saxena, and Kenneth Butler. Bridging Fault Diagnosis in the Absence of Physical Information. In Proceedings of the International Test Conference, pages 887-893, 1997.
D. B. Lavo, T. Larrabee, and B. Chess, Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis. In Proceedings of the International Test Conference, pages 611-619, 1996.
B. Chess, D. B. Lavo, F.J. Ferguson, and T. Larrabee. Diagnosis of Realistic Bridging Faults with Single Stuck-at Information. In Proceedings of the International Conference on Computer Aided Design, pages 185-192, 1995.
B. Chess, Diagnostic Test Pattern Generation and the Creation of Small Full Dictionaries. Masters Thesis, University of California at Santa Cruz, Department of Computer Engineering, June 1995. B. Chess, A Freitas, F.J. Ferguson, and T. Larrabee. Testing CMOS Logic Gates for Realistic Shorts. In Proceedings of the International Test Conference, pages 395-401, 1994. B. Chess, T. Larrabee, and C. Roth. On Evaluating competing bridge fault models for CMOS ICs. In Proceedings of the 12th VLSI Test Symposium, pages 446-451, 1994. B. Chess and T. Larrabee. Generating test patterns for bridge faults in CMOS ICs. In Proceedings of the European Test Conference, pages 165-170, 1994. B. Chess and T. Larrabee. Bridge Fault Simulation Strategies for CMOS Integrated Circuits. In Proceedings of the Design Automation Conference, pages 458-462, 1993.